450NX Datasheet, PDF (77/248 Pages) Intel Corporation – Intel 450NX PCIset

3.4 PXB Configuration Space
3.4.28 ROUTE: Route Field Seed
Address Offset: C3h
Default Value: 73h (A-side space)
62h (B-side space)
Bits Description
Size:
8 bits
Attribute: Read/Write
7:4 Inbound-to-Host-Bus Route Seed.
This field represents the "seed" value used to create the routing field for packets
inbound to the system bus (i.e., third-party).
Default: 0111b (A-side configuration space)
0110b (B-side configuration space)
3:0 Inbound-to-Memory Route Seed.
This field represents the "seed" value used to create the routing field for packets
inbound to memory.
Default: 0011b (A-side configuration space)
0010b (B-side configuration space)
3.4.29 SMRAM: SMM RAM Control Register
Address Offset: 6C-6Fh
Default Value: 00000Ah
Size:
32 bits
Attribute: Read/Write
This register defines the System Management Mode RAM address range, and enables the
control access into that range. Fields of this register which exist in the MIOC SMRAM register
must be programmed to the same values.
Bits Description
31
SMRAM Enable (SMRAME).
If set, the SMRAM space is protected from inbound PCI bus access. If clear, this
register has no effect on inbound memory accesses.
Default=0.
30:24 reserved (0)
23:20
SMM Space Size.
This field specifies the size of the SMM RAM space, in 64 KB increments.
0h 64 KB
1h 128 KB
2h 192 KB
3h 256 KB
4h 320 KB
5h 384 KB
6h 448 KB
7h 512 KB
8h 576 KB
9h 640 KB
Ah 704 KB
Bh 768 KB
Ch 832 KB
Dh 896 KB
Eh 960 KB
Fh 1 MB
Default: 0h (64 KB).
19:16 reserved (0)
15:0 SMM Space Base Address.
This field specifies the A[31:16] portion of the SMM RAM space base address
(A[15:0]=0000h). The space may be relocated anywhere below the 4 GB boundary
Intel® 450NX PCIset
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