450NX Datasheet, PDF (39/248 Pages) Intel Corporation – Intel 450NX PCIset

3.3 MIOC Configuration Space
12
Outbound Fairness Disable.
When this bit is clear, Host-PCI writes and reads that receive a retry by the MIOC
follow a fairness algorithm to guarantee that retried transactions receive first priority
before new transactions. If set, Host-PCI writes and reads are serviced in the order
first observed without regard to retry history. Default=1.
11
Performance Counter Master Enable (PCME).
This bit provides a mechanism to (nearly) simultaneously freeze or start the
performance counters across both the MIOC and PXBs.
If this bit is cleared the MIOC’s and PXB’s performance counters will not increment
If set the MIOC’s and PXB’s performance counters resume normal operation.
Default = 0.
10
reserved (0)
9
Third Party Support Disable
If set, performance optimizations are enabled that may result in coherency violations
in the presence of a third party agent. This bit should be clear for systems with TPAs.
Default = 0.
8
External Arbiter Enable.
If set, access to the system bus is controlled by an external arbiter. If cleared, the
MIOC’s internal arbiter is used. Default=0.
7
WC Write Post During I/O Bridge Access Enable (UWPE).
This bit should be cleared for normal operation. Default=0.
6
Outbound I/O Write Posting Enable.
If set, Host-PCI I/O writes will be posted. If cleared, Host-PCI I/O writes will not be
posted. In normal operation, this enable should be set. Default=0.
5
Read-Around-Write Enable (RAWE).
If RAWE is set, it enables the read-around-write capability for the MIOC and memory
subsystem. If cleared, read accesses will not advance past any previously posted
writes. In normal operation, this enable should be set. Default=0.
4
ISA Expansion Aliasing Enable.
If set, every I/O access with an address in the range x100-x3FFh, x500-x7FFh, x900-
xBFF and xD00-xFFFh is internally aliased to the range 0100-03FFh before any other
address range checking is performed. This bit only affects routing, the unmasked
address is passed to the PCI bus. Default=0.
3
reserved (0)
2
Card to Card Interleave Enable.
If set, Host or PCI accesses to memory are distributed to both memory cards on a
cache line granularity. This provides a performance enhancement for systems which
utilize two memory cards. When this bit is clear, C2C interleaving is disabled. Default
= 0.
Intel® 450NX PCIset
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