450NX Datasheet, PDF (144/248 Pages) Intel Corporation – Intel 450NX PCIset

12. Electrical Characteristics
HCLK
1P Launched Here 1P Sampled Here
1P Capture Range
T20
Data
STRB
1P
1N
ODD
2P
2N
EVEN
3P
3N
ODD
Figure 12-9: Source Synchronous Data Transfer
12.5 Source Synchronous Data Transfers
A Source Synchronous packet has a two clock period delivery time, and is divided into
positive and negative phases of even and odd cycles. During this two clock window, packets
are launched synchronously and sampled synchronously. Signals launched with a positive
phase “even” clock are sampled on a positive phase of next “even” clock. Between launch and
sample, signals are captured with source synchronous strobes.
HCLKIN
V
Ts =Setup Time
Th = Hold Time
V =1.0V for AGTL+
1.5V for 3.3V-tolerant CMOS
1.25V for 2.5V CMOS
Figure 12-10: Setup and Hold Timings
Ts
Th
VALID
1.25V
12-20
Intel® 450NX PCIset