450NX Datasheet, PDF (37/248 Pages) Intel Corporation – Intel 450NX PCIset

3.3 MIOC Configuration Space
3.3.2
BUSNO[1:0]: Lowest PCI Bus Number, per PXB
Address Offset: D0h, D3h
Default Value: 00h each
Size:
8 bits each
Attribute: Read/Write
The MIOC supports two Expander Ports; each can support one PXB. PXB #0 is connected to
Expander Port #0, and PXB #1 is connected to Expander Port #1. Each PXB supports one or
two PCI buses, connected to PCI Ports “A” and “B”. The PCI bus connected to Port #0A must
be the compatibility PCI bus from which a system boots.
Three registers (BUSNO, SUBA and SUBB) define the bus hierarchy for each PXB.
BUSNO[0]
Holds the PCI-bus-number of the bus connected to PXB #0 Bus #A. This must
be set to 0.
SUBA[0]
Holds the PCI-bus-number of the highest subordinate bus under PXB #0 Bus
#A. The PCI bus number for PXB #0 Bus #B is SUBA[0]+1.
SUBB[0]
Holds the PCI-bus-number of the highest subordinate bus under PXB #0 Bus
#B. This also represents the highest PCI-bus-number accessible from PXB #0.
BUSNO[1]
Holds the PCI-bus-number of the bus connected to PXB #1 Bus #A.
SUBA[1]
Holds the PCI-bus-number of the highest subordinate bus under PXB #1 Bus
#A. The PCI bus number for PXB #1 Bus #b is SUBA[1]+1.
SUBB[1]
Holds the PCI-bus-number of the highest subordinate bus under PXB #1 Bus
#B. This also represents the highest PCI-bus-number accessible from PXB #1
(and therefore the Intel 450NX PCIset). If PXB#1 is not in use, program this
register to 0.
If PXB i is operating in 64-bit bus mode, SUBB[i] must equal SUBA[i].
Bits Description
7:0 PCI Bus Number.
NOTE
Inactive PXBs should be disabled by writing the corresponding Reset Expander Port bit in the RC
register and resetting the corresponding "Device present" bit in the DEVMAP register.
3.3.3
CHKCON: Check Connection
Address Offset: 43h
Default Value: 10h
Size:
8 bits
Attribute: Read/Write
Bits Description
7:6 reserved
Intel® 450NX PCIset
3-5