450NX Datasheet, PDF (121/248 Pages) Intel Corporation – Intel 450NX PCIset

11.2 System Reset
Third-Party Agent Interface
IOGNT#
-
TPCTL[1:0]
IOREQ#
Tristate
Memory Subsystem / External Interface
BANK[2:0]#
Deasserted DVALID(a,b)#
CARD[1:0]#
Deasserted MA[13:0]#
CMND[1:0]#
Deasserted MD[71:0]#
CSTB#
Deasserted MRESET#
DCMPLT(a,b)#
Tristate PHIT(a,b)#
DOFF[1:0]#
Deasserted ROW#
DSEL[1:0]#
Deasserted RCMPLT(a,b)#
DSTBN[3:0]#
Tristate RHIT(a,b)#
DSTBP[3:0]#
Tristate WDEVT#
Expander Interface (two per MIOC: 0,1)
X(0,1)ADS#
Tristate X(0,1)HSTBP#
X(0,1)BE[1:0]#
Tristate X(0,1)PAR#
X(0,1)BLK#
Deasserted X(0,1)RST#
X(0,1)CLK
Toggling X(0,1)RSTB#
X(0,1)CLKB
Toggling X(0,1)RSTFB#
X(0,1)CLKFB
-
X(0,1)XRTS#
X(0,1)D[15:0]#
Tristate X(0,1)XSTBN#
X(0,1)HRTS#
Toggling X(0,1)XSTBP#
X(0,1)HSTBN#
Toggling
Common Support Signals
CRES[1:0]
Strapped TMS
TCK
-
TRST#
TDI
-
VCCA (3)
TDO
OD
VREF (6)
Component-Specific Support Signals
CRESET#
Asserted PWRGD
ERR[1:0]#
Tristate
PWRGDB
HCLKIN
Toggling RESET#
INTREQ#
Deasserted SMIACT#
-
Deasserted
Deasserted
Tristate
Asserted
-
Deasserted
-
-
Deasserted
Toggling
Tristate
Asserted
Asserted
-
-
-
-
-
-
Reference
Reference
-⁴
De/asserted⁴
Asserted
Deasserted
Notes:
1. The Pentium^® II Xeon™ processor allows for configuring a variety of processor and bus variables during the reset sequence.
During RESET# assertion, and for one clock past the trailing edge of RESET#, the Intel 450NX PCIset MIOC will drive the
contents of its CVDR register onto A[15:3]#. All system bus devices (including the MIOC) are required to sample these address
lines using the trailing edge of reset, and modify their internal configuration accordingly. Note the initial value of CVDR may be
changed by the boot processor, and the reset process re-engaged. This allows the processors and buses to power-up in a “safe”
state, yet allow re-configuration based on specific system constraints.
2. BREQ0# must stay asserted (low) for a minimum of 2 system clocks after the rising edge of RESET#. The MIOC then releases
(tristates) the BREQ0# signal.
3. INIT# is not asserted during power-up. It may be optionally asserted during system hard reset through the RC register to cause
the processors to initiate BIST.
4. The PWRGDB output is asserted if the PWRGD input is asserted (i.e., a power-good reset). For a system hard reset, the
PWRGDB output is deasserted.
Intel® 450NX PCIset
11-7