450NX Datasheet, PDF (11/248 Pages) Intel Corporation – Intel 450NX PCIset

1.3 Intel^® 450NX PCIset Feature Summary
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Intel^® 450NX PCIset Feature Summary
System Bus Support
• Fully supports the Pentium^® II Xeon™ processor bus protocol at bus frequencies up to
100 MHz.
• Functionally and electrically compatible with the original and Pentium II P6 family
processor buses.
• Fully supports 4-way multiprocessing, with performance scaling to 3.5x that of a uni-
processor system.
• Full 36-bit address decode and drive capability.
• Full 64-bit data bus (32-bit data bus mode is not supported).
• Parity protection on address and control signals, ECC protection on data signals.
• 8-deep in-order queue; 24-deep memory request queue; 2-deep outbound read-request
queue per PCI bus; 6-deep outbound write-posting queue per PCI bus.
• AGTL+ bus driver technology.
• Intel^® 450NX PCIset adds only one load to the system bus.
• Intel 450GX PCIset-compatible third-party request/grant and control signals, allowing
cluster bridges to be placed on the system bus.
DRAM Interface Support
• Memory technologies supported are 16- and 64-Mbit, 60nsec and 50nsec 3.3v EDO DRAM
devices.
• Supports from 32 MB to 8 GB of memory, in 64 MB increments after the initial 32 MB.
• Supports 4-way interleaved operation, with 2-way interleave supported in the first bank
of card 0 to permit entry-level systems with minimal memory.
• Supports memory address bit permuting (ABP) to obtain alternate row selection bits.
• Supports card-to-card interleaving to further distribute memory accesses across multiple
banks of memory.
• Staggered CAS-before-RAS refresh.
• ECC with single-bit error correction and scrub-on-error in the memory.
• Extensive Host-to-Memory and PCI-to-Memory write data buffering.
I/O Bridge Support
• Up to four independent 32-bit PCI ports (using two PXBs)
– each supports up to 10 electrical loads (connectors count as loads).
– each provides internal arbitration for up to 6 masters plus a south bridge on the
compatibility PCI bus, or external arbitration.
• Synchronous operation to the system bus clock using a 3:1 system bus/PCI bus gearing
ratio.
– 3:1 ratio supports a 100 MHz system bus and 33.33 MHz PCI bus.
– 3:1 ratio supports a 90 MHz system bus and 30 MHz PCI bus (or lower, depending on
effect of 6th load).
• Parity protection on all PCI signals.
• Inbound read prefetches of up to 4 cache lines.
• Outbound write assembly of full/partial line writes.
• Data streaming support from PCI to DRAM.
Intel® 450NX PCIset
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