450NX Datasheet, PDF (71/248 Pages) Intel Corporation – Intel 450NX PCIset

3.4 PXB Configuration Space
3.4.19 MMT: Memory-Mapped PCI Top
Address Offset: 7A-7Bh
Default Value: 0001h
Size:
16 bits
Attribute: Read/Write
This register defines the highest address of the memory-mapped PCI space. See the MMBASE
register above for a detailed description. The MMT register must be programmed identically
to MMR[3] in the MIOC to achieve correct functioning.
3.4.20 MTT: Multi-Transaction Timer Register
Address Offset: 43h
Default Value: 00h
Size:
8 bits
Attribute: Read/Write
This register controls the amount of time that the PCI bus arbiter allows a PCI initiator to
perform multiple back-to-back transactions on the PCI bus.
Bits Description
7:3 MTT Count Value.
Specifies the guaranteed time slice (in 8-PCI-clock increments) allotted to the current
agent, after which the PXB will grant the bus as soon as other PCI masters request the
bus. A value of 0 disables this function. Default=0.
2:0 reserved (0)
3.4.21 PCICMD: PCI Command Register
Address Offset: 04 - 05h
Default Value: 0016h
Size:
16 bits
Attribute: Read/Write, Read-Only
This is a PCI specification required register with a fixed format.
Bits Description
15:10 reserved (0)
9
Fast Back-to-Back.
Fast back-to-back cycles are not implemented by the PXB, and this bit is hardwired to
0.
8
SERR# Enable (SERRE).
If this bit is set, the PXB’s SERR# signal driver is enabled and SERR# is asserted for
all relevant bits set in the ERRSTS and PCISTS as controlled by the corresponding
bits of the ERRCMD register. If SERRE is set and the PXB’s PCI parity error reporting
is enabled by the PERRE bit, then the PXB will assert SERR# on address parity
errors. Default=0.
Intel® 450NX PCIset
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