450NX Datasheet, PDF (53/248 Pages) Intel Corporation – Intel 450NX PCIset

3.3 MIOC Configuration Space
3.3.29 MMBASE: Memory-Mapped PCI Base
Address Offset: 70-71h
Default Value: 0002h
Size:
16 bits
Attribute: Read/Write
The MMBASE register defines the starting address of the Memory-Mapped PCI Space, and
each MMR register defines the highest address to be directed to a PCI bus.
If PXB 0 is operating in 64-bit bus mode, MMR[0] must equal MMBASE.
If PXB 1 is operating in 64-bit bus mode, MMR[3] must equal MMR[2].
Bits Description
15:12 reserved (0)
11:0 PCI Space Base Address.
This field specifies the A[31:20] portion of the PCI space’s base address, in 1MB
increments. The A[43:32] and A[19:0] portions of the address are zero.
3.3.30 MMR[3:0]: Memory-Mapped PCI Ranges
Address Offset: 74-7Bh
Default Value: 0001h each
Size:
16 bits each
Attribute: Read/Write
These registers define the high addresses for addresses to be directed to the PCI space.
Bits Description
15:12 reserved (0)
11:0 PCI Space Top Address.
This field specifies the A[31:20] portion of the PCI space’s highest address, in 1 MB
increments. The A[43:32] portion of this address is zero, while the A[19:0] portion of
this address is FFFFFh.
3.3.31 PMD[1:0]: Performance Monitoring Data Register
Address Offset: D8-DCh, E0-E4h
Default Value: 0000000000h each
Size:
40 bits each
Attribute: Read/Write
Two performance monitoring counters are provided in the MIOC. The PMD registers hold the
performance monitoring count values. Each counter can be configured to reload the data
when it, or the other counter overflows.
Event selection is controlled by the PME registers, and the action performed on event
detection is controlled by the PMR registers. An additional Performance Counter Master Enable
(PCME) in the MIOC’s CONFIG register allows (nearly) simultaneous stopping/starting of all
counters in the MIOC and each PXB. The counters cannot be read or written coherently while
the counters are running.
Intel® 450NX PCIset
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