450NX Datasheet, PDF (72/248 Pages) Intel Corporation – Intel 450NX PCIset

3. Register Descriptions
7
Address/Data Stepping.
The PXB does not support address/data stepping, and this bit is hardwired to 0.
6
Parity Error Response (PERRE).
If PERRE is set, the PXB will report parity errors on data received by asserting the
PERR# signal. Address parity errors are not reported using PERR#, but instead
through the SERR# signal, and only if both PERRE and SERRE are set. If PERRE is
cleared, then PCI parity errors are not reported by the PXB. Default=0.
5
reserved (0)
4
Memory Write and Invalidate Enable.
Selects whether the PXB, as a PCI master, can generate Memory Write and Invalidate
cycles. Default=1.
3
Special Cycle Enable.
The PXB will ignore all special cycles generated on the PCI bus, and this bit is
hardwired to 0.
2
Bus Master Enable.
The PXB does not permit disabling of its bus master capability, and this bit is
hardwired to 1.
1
Memory Access Enable.
The PXB does not permit disabling access to main memory, and this bit is hardwired
to 1.
0
I/O Access Enable.
The PXB does not respond to PCI I/O cycles, and this bit is hardwired to 0.
3.4.22 PCISTS: PCI Status Register
Address Offset: 06 - 07h
Default Value: 0280h
Size:
16 bits
Attribute: Read/Write Clear, Sticky
This is a PCI specification required register, with a fixed format.
Bits Description
15
Parity Error (PE).
This bit is set when the PXB detects a parity error in data or address on the PCI bus.
This bit remains set until explicitly cleared by software writing a 1 to this bit.
Default=0.
14
Signaled System Error (SSE).
This bit is set when the PXB asserts the SERR# signal. This bit remains set until
explicitly cleared by software writing a 1 to this bit.
Default=0.
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Intel® 450NX PCIset