450NX Datasheet, PDF (105/248 Pages) Intel Corporation – Intel 450NX PCIset

Arbitration, Buffers & Concurrency ₈
8.1
PCI Arbitration Scheme
The PCI Specification Rev 2.1 requires that the arbiter implement a fairness algorithm to avoid
deadlocks and that it assert only a single GNT# signal on any rising clock. The arbitration
algorithm is fundamentally not part of the PCI Specification.
The PXB contains an internal PCI arbiter. This arbiter can be disabled either when the PXB
operates with I/O bridges which include this function, or when a customized PCI arbiter
solution is required. The Internal PCI Arbiter has the following features:
• Support for 6 PCI masters, Host and I/O Bridge
• 2 Level Round Robin
• Bus Lock Implementation
• Bus Parking on last agent using the bus
• 4-PCI clock grant (FRAME#) time-out
• Multi Transaction Timer (MTT) mechanism
• PCI arbitration is independent from the system bus arbitration
• PIIX4E- compatible protocol (EISA bridges are not supported)
• PCI Protocol Requirements
8.2
Host Arbitration Scheme
The system bus arbitration protocol supports two classes of bus agents: symmetric agents and
priority agents. The processors arbitrate for the system bus as symmetric agents using their
own signaling. Symmetric agents implement fair, distributed arbitration using a round-robin
algorithm. The MIOC, as an I/O agent, uses a priority agent arbitration protocol to obtain the
ownership of the system bus. Priority agents use the BPRI# signal to immediately obtain bus
ownership.
Besides two classes of arbitration agents (symmetric and priority agents), each bus agent has
two mechanisms available that act as arbitration modifiers: the bus lock (LOCK#) and the
request stall (BNR#).
Intel® 450NX PCIset
8-1