450NX Datasheet, PDF (94/248 Pages) Intel Corporation – Intel 450NX PCIset

6. Memory Subsystem
Pentium^® II Xeon™ processor system bus
addr[35:0], data[71:0] & ctrls
MD[71:0]
memory cards
MIOC
Memory
Control
Interface
MUXs ^2x36
72
36 36
to PCI via
Expander bridge
Card 0
Figure 6-1: Memory Configuration Using 2 Cards
rows
bank
Card 1
To/From MIOC
Memory Array
RASA[a:d][1:0]#, CASA[a:d][1:0]#, WEA[a:b]#
ADDRA[13:0]
Bank A
RASB[a:d][1:0]#, CASB[a:d][1:0]#, WEB[a:b]#
ADDRB[13:0]
RCG
#0
RASC[a:d][1:0]#, CASC[a:d][1:0]#, WEC[a:b]#
ADDRC[13:0]
Bank B
Bank C
To/From Other RCGs
RASD[a:d][1:0]#, CASD[a:d][1:0]#, WED[a:b]#
ADDRD[13:0]
AVWP#
LDSTB#
LRD#
WDME#
GDCMPLT#
To/From Other MUXs
Bank D
MUXs (2)
DOFF[1:0]#
DSEL#
DVALID[a:b]#
WDEVT#
DCMPLT[a:b]#
DSTBP[3:0]#
DSTBN[3:0]#
From MIOC To/From MIOC
Figure 6-2: Example Showing RCG/MUX Control Signals
6-2
Intel® 450NX PCIset