MC912DG128ACPVE Datasheet, PDF (90/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Resource Mapping
6.3.2 RAM Mapping
The MC68HC912DT128A has 8K bytes of fully static RAM that is used
for storing instructions, variables, and temporary data during program
execution. Since the RAM is actually implemented with two 4K RAM
arrays, any misaligned word access between last address of first 4K
RAM and first address of second 4K RAM will take two cycles instead of
one. After reset, RAM addressing begins at location $2000 but can be
assigned to any 8K byte boundary within the standard 64K byte address
space. Mapping of internal RAM is controlled by three bits in the INITRM
register.
INITRM — Initialization of Internal RAM Position Register
$0010
Bit 7
6
5
4
3
2
1
Bit 0
RAM15 RAM14 RAM13
0
0
0
0
0
RESET:
0
0
1
0
0
0
0
0
RAM[15:13] — Internal RAM map position
These bits specify the upper three bits of the 16-bit RAM address.
Normal modes: write once; special modes: write anytime. Read
anytime.
Technical Data
90
MC68HC912DT128A — Rev 4.0
Resource Mapping
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