MC912DG128ACPVE Datasheet, PDF (310/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Inter IC Bus
Freescale Semiconductor, Inc.
IBC2-0
(bin)
000
001
010
011
100
101
110
111
Table 17-1. IIC Tap and Prescale Values
SCL Tap SDA Tap
(clocks) (clocks)
5
1
6
1
7
2
8
2
9
3
10
3
12
4
15
4
IBC5-3
(bin)
000
001
010
011
100
101
110
111
scl2tap
(clocks)
4
4
6
6
14
30
62
126
tap2tap
(clocks)
1
2
4
8
16
32
64
128
The number of clocks from the falling edge of SCL to the first tap
(Tap[1]) is defined by the values shown in the scl2tap column of Table
17-1, all subsequent tap points are separated by 2^IBC5-3 as shown in
the tap2tap column in Table 17-1. The SCL Tap is used to generated
the SCL period and the SDA Tap is used to determine the delay from
the falling edge of SCL to SDA changing, the SDA hold time.
The serial bit clock frequency is equal to the CPU clock frequency
divided by the divider shown in Table 17-2. The equation used to
generate the divider values from the IBFD bits is:
SCL Divider = 2 x ( scl2tap + [ ( SCL_Tap -1 ) x tap2tap ] + 2 )
The SDA hold delay is equal to the CPU clock period multiplied by the
SDA Hold value shown in Figure 17-2. The equation used to generate
the SDA Hold value from the IBFD bits is:
SDA Hold = scl2tap + [ ( SDA_Tap - 1 ) x tap2tap ] + 3
Technical Data
310
MC68HC912DT128A — Rev 4.0
Inter IC Bus
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