MC912DG128ACPVE Datasheet, PDF (323/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Inter IC Bus
Freescale Semiconductor, Inc.
Clear
IBIF
Y
Master
N
Mode
?
TX
Tx/Rx
RX
?
Last Byte
Transmitted Y
?
N
Clear IBAL
Y
Arbitration
Lost
?
N
RXAK=0
?
N
Y
Last
Byte To Be Read
?
Y
N
Y
End Of
Addr Cycle
(Master Rx)
?
N
Y
2nd Last
Byte To Be Read
?
N
Write Next
Byte To IBDR
Set TXAK =1
Generate
Stop Signal
N
(ReaYd)
IAAS=1
?
Y _IAAS=1
?
Y
N
Address Transfer
Data Transfer
SRW=1
?
N ^(Write)
TX/RX
RX
?
TX
Set TX
Mode
Write Data
To IBDR
Y ACK From
Receiver
?
N
Tx Next
Byte
Read Data
From IBDR
And Store
Switch To
Rx Mode
Set RX
Mode
Switch To
Rx Mode
Dummy Read
From IBDR
Generate
Stop Signal
Read Data
From IBDR
And Store
Dummy Read
From IBDR
Dummy Read
From IBDR
RTI
Figure 17-4. Flow-Chart of Typical IIC Interrupt Routine
Technical Data
323
MC68HC912DT128A — Rev 4.0
Inter IC Bus
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