MC912DG128ACPVE Datasheet, PDF (304/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Inter IC Bus
Freescale Semiconductor, Inc.
17.4 IIC System Configuration
The IIC system uses a Serial Data line (SDA) and a Serial Clock Line
(SCL) for data transfer. All devices connected to it must have open drain
or open collector outputs. Logic “and” function is exercised on both lines
with external pull-up resistors, the value of these resistors is system
dependent.
17.5 IIC Protocol
Normally, a standard communication is composed of four parts: START
signal, slave address transmission, data transfer and STOP signal. They
are described briefly in the following sections and illustrated in Figure 17-
2.
MSB
LSB
SCL
1 2 34 5 6 78 9
MSB
LSB
1 2 34 5 6 78 9
SDA
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XXX D7 D6 D5 D4 D3 D2 D1 D0
Start
Signal
Calling Address
Read/ Ack
Write ^Bit
MSB
LSB
SCL
1 2 34 5 67 89
Data Byte
No Stop
Ack Signal
Bit
MSB
LSB
1 234 5 678 9
SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XX
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Start
Signal
Calling Address
Read/ Ack
Write ^Bit
Repeated
Start
Signal
New Calling Address
Read/ No Stop
Write
Ack Signal
Bit
Figure 17-2. IIC Transmission Signals
Technical Data
304
MC68HC912DT128A — Rev 4.0
Inter IC Bus
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