MC912DG128ACPVE Datasheet, PDF (384/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Analog-to-Digital Converter
Table 19-5. Clock Prescaler Values
Prescale
Value
00000
00001
00010
00011
00100
00101
00110
00111
01xxx
1xxxx
Total Divisor
÷2
÷4
÷6
÷8
÷10
÷12
÷14
÷16
Max PCLK⁽¹⁾
4 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
Do Not Use
Min PCLK⁽²⁾
1 MHz
2 MHz
3 MHz
4 MHz
5 MHz
6 MHz
7 MHz
8 MHz
1. Maximum conversion frequency is 2 MHz. Maximum PCLK divisor value will become
maximum conversion rate that can be used on this ATD module.
2. Minimum conversion frequency is 500 kHz. Minimum PCLK divisor value will become
minimum conversion rate that this ATD can perform.
19.9.4 ATDCTL5 ATD Control Register 5
ATD control register 5 determines the type of conversion sequence and
the analog input channels sampled. All writes to this register have an
immediate effect. If a conversion is in progress, the entire conversion
sequence is aborted. A write to this register (or ATDCTL4) initiates a new
conversion sequence (SCF and CCF bits are reset).
ATD0CTL5/ATD1CTL5 — ATD Control Register 5
$0065/$01E5
Bit 7
6
5
4
3
2
1
Bit 0
0
S8C
SCAN
MULT
SC
CC
CB
CA
RESET:
0
0
0
0
0
0
0
0
S8C / S1C — Conversion Sequence Length
S8C: Bit Position: 6, ATDCTL5
S1C: Bit Position: 3, ATDCTL3
The S8C/S1C bits define the length of a conversion sequence. Table
19-6 lists the coding combinations.
Technical Data
384
MC68HC912DT128A — Rev 4.0
Analog-to-Digital Converter
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