MC912DG128ACPVE Datasheet, PDF (449/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Appendix: CGM Practical Aspects
Practical Aspects For The PLL Usage
acquisition (AUTO=0, ACQ=0 in the PLLCR register).
In both equations, the power supply should be 5V. Start with the target
loop bandwidth as a function of the other parameters, but obviously,
nothing prevents the user from starting with the capacitor value for
example. Also, remember that the smoothing capacitor is always
assumed to be one tenth of the series capacitance value.
So with:
m:
R:
C:
F_bus:
ζ:
F_c:
the multiplying factor for the reference frequency (i.e. (synr+1))
the series resistance of the low pass filter in Ω
the series capacitance of the low pass filter in nF
the target bus frequency expressed in MHz
the desired damping factor
the desired loop bandwidth expressed in Hz
for the ‘tracking’ mode:
F_c
=
2-----⋅_---1---0---⁹_----⋅_---ζ_---²_-
π⋅R⋅C
=
-3--7---.--7---8-----^â‹---e--^⎝⎛--^1--^--^-.--^--^6--^-1--^7--^-0--^5--^-.-^--7-^-–-^--9-^--^-F-5-^--^--^-b--^-u-^---^-s-^⎠⎞----^â‹---R--
2⋅π⋅m
and for the ‘acquisition’ mode:
F_c
=
2-----⋅_---1---0---⁹_----⋅_---ζ_---²_-
π⋅R⋅C
=
4----1---5---.-6---1----⋅_----e--^⎝⎛_--^1-_-^-_-^-.-_-^-_-^6-_-^-1-_-^7-_-^-0-_-^5-_-^-._-^--7_-^–-_-^--9_-^-_-^-F-5_-^-_-^-_-^-b-_-^-u_-^--_-^-s_-^⎠⎞_----⋅_---R--
2⋅π⋅m
23.3.3.2 Particular Case of an 8MHz Synthesis
Assume that a desired value for the damping factor of the second order
system is close to 0.9 as this leads to a satisfactory transient response.
Then, derived from the equations above, Table 23-1 and Table 23-2
suggest sets of values corresponding to several loop bandwidth
possibilities in the case of an 8MHz synthesis for the two cases
mentioned above.
MC68HC912DT128A — Rev 4.0
MOTOROLA
Appendix: CGM Practical Aspects
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Technical Data
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