MC912DG128ACPVE Datasheet, PDF (185/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Clock Functions
Computer Operating Properly (COP)
PCLK
5-BIT MODULUS
COUNTER (PR0-PR4)
÷2
÷ 2 REGISTER: SP0BR
BITS: SPR2, SPR1, SPR0
0:0:0
÷2
0:0:1
SPI
BIT RATE
EXTALi
÷2
0:1:0
CLKSRC
÷2
0:1:1
SYSCLK
TO ATD0
and ATD1
MSCAN
CLOCK
÷2
1:0:0
÷2
1:0:1
÷2
1:1:0
÷2
1:1:1
ECLK
BCLK
CLKSW
SYNCHRONIZER
BKGD IN
BKGD
PIN
LOGIC
BKGD DIRECTION
BKGD OUT
BDM BIT CLOCK:
Receive: Detect falling edge,
count 12 E clocks, Sample input
Transmit 1: Detect falling edge,
count 6 E clocks while output is
high impedance, Drive out 1 E
cycle pulse high, high imped-
ance output again
Transmit 0: Detect falling edge,
Drive out low, count 9 E clocks,
Drive out 1 E cycle pulse high,
high impedance output
Figure 12-9. Clock Chain for MSCAN, SPI, ATD0, ATD1 and BDM
12.9 Computer Operating Properly (COP)
The COP or watchdog timer is an added check that a program is running
and sequencing properly. When the COP is being used, software is
responsible for keeping a free running watchdog timer from timing out. If
the watchdog timer times out it is an indication that the software is no
longer being executed in the intended sequence; thus a system reset is
initiated. Three control bits allow selection of seven COP time-out
periods. When COP is enabled, sometime during the selected period the
program must write $55 and $AA (in this order) to the COPRST register.
If the program fails to do this the part will reset. If any value other than
$55 or $AA is written, the part is reset.
MC68HC912DT128A — Rev 4.0
MOTOROLA
Clock Functions
For More Information On This Product,
Go to: www.freescale.com
Technical Data
185