MC912DG128ACPVE Datasheet, PDF (123/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Technical Data — MC68HC912DT128A
Section 9. EEPROM Memory
9.1 Contents
9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.3 EEPROM Selective Write More Zeros . . . . . . . . . . . . . . . . . .124
9.4 EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . .125
9.5 EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9.6 Program/Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9.7 Shadow Word Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
9.8 Programming EEDIVH and EEDIVL Registers. . . . . . . . . . . . 135
9.2 Introduction
The MC68HC912DT128A EEPROM nonvolatile memory is arranged in
a 16-bit configuration. The EEPROM array may be read as either bytes,
aligned words or misaligned words. Access times are one bus cycle for
byte and aligned word access and two bus cycles for misaligned word
operations.
Programming is by byte or aligned word. Attempts to program or erase
misaligned words will fail. Only the lower byte will be latched and
programmed or erased. Programming and erasing of the user EEPROM
can be done in normal modes.
Each EEPROM byte or aligned word must be erased before
programming. The EEPROM module supports byte, aligned word, row
(32 bytes) or bulk erase, all using the internal charge pump. The erased
state is $FF. The EEPROM module has hardware interlocks which
protect stored data from corruption by accidentally enabling the
program/erase voltage. Programming voltage is derived from the
internal V_DD supply with an internal charge pump.
MC68HC912DT128A — Rev 4.0
Technical Data
MOTOROLA
EEPROM Memory
123
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