MC912DG128ACPVE Datasheet, PDF (350/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
MSCAN Controller
18.12.4 Data Segment Registers (DSRn)
The eight data segment registers contain the data to be transmitted or
being received. The number of bytes to be transmitted or being received
is determined by the data length code in the corresponding DLR.
18.12.5 Transmit Buffer Priority Registers (TBPR)
TBPR^{(1) R}
$01xD W
RESET
BIT 7
PRIO7
-
BIT 6
PRIO6
-
BIT 5
PRIO5
-
BIT 4
PRIO4
-
BIT 3
PRIO3
-
1. x is 5, 6, or 7 depending on which buffer Tx0, Tx1, or Tx2 respectively.
BIT 2
PRIO2
-
BIT 1
PRIO1
-
BIT 0
PRIO0
-
PRIO7 – PRIO0 — Local Priority
This field defines the local priority of the associated message buffer.
The local priority is used for the internal prioritizing process of the
msCAN12 and is defined to be highest for the smallest binary number.
The msCAN12 implements the following internal priorization
mechanism:
• All transmission buffers with a cleared TXE flag participate in the
priorisation right before the SOF (Start of Frame) is sent.
• The transmission buffer with the lowest local priority field wins the
priorisation.
• In case of more than one buffer having the same lowest priority the
message buffer with the lower index number wins.
NOTE:
To ensure data integrity, no registers of the transmit buffers shall be
written while the associated TXE flag is cleared.
To ensure data integrity, no registers of the receive buffer shall be read
while the RXF flag is cleared.
Technical Data
350
MC68HC912DT128A — Rev 4.0
MSCAN Controller
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