MC912DG128ACPVE Datasheet, PDF (306/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Inter IC Bus
Freescale Semiconductor, Inc.
Each data byte is 8 bits long. Data may be changed only while SCL is
low and must be held stable while SCL is high as shown in Figure 17-2.
There is one clock pulse on SCL for each data bit, the MSB being
transferred first. Each data byte has to be followed by an acknowledge
bit, which is signalled from the receiving device by pulling the SDA low
at the ninth clock. So one complete data byte transfer needs nine clock
pulses.
If the slave receiver does not acknowledge the master, the SDA line
must be left high by the slave. The master can then generate a stop
signal to abort the data transfer or a start signal (repeated start) to
commence a new calling.
If the master receiver does not acknowledge the slave transmitter after
a byte transmission, it means 'end of data' to the slave, so the slave
releases the SDA line for the master to generate STOP or START signal.
17.5.4 STOP Signal
The master can terminate the communication by generating a STOP
signal to free the bus. However, the master may generate a START
signal followed by a calling command without generating a STOP signal
first. This is called repeated START. A STOP signal is defined as a low-
to-high transition of SDA while SCL at logical “1” (see Figure 17-2).
The master can generate a STOP even if the slave has generated an
acknowledge at which point the slave must release the bus.
17.5.5 Repeated START Signal
As shown in Figure 17-2, a repeated START signal is a START signal
generated without first generating a STOP signal to terminate the
communication. This is used by the master to communicate with another
slave or with the same slave in different mode (transmit/receive mode)
without releasing the bus.
Technical Data
306
MC68HC912DT128A — Rev 4.0
Inter IC Bus
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