MC912DG128ACPVE Datasheet, PDF (295/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Multiple Serial Interface
Serial Peripheral Interface (SPI)
1 = Hardware interrupt sequence is requested each time the SPIF
or MODF status flag is set
SPE — SPI System Enable
0 = SPI internal hardware is initialized and SPI system is in a low-
power disabled state.
1 = PS[4:7] are dedicated to the SPI function
When MODF is set, SPE always reads zero. SP0CR1 must be written
as part of a mode fault recovery sequence.
SWOM — Port S Wired-OR Mode
Controls not only SPI output pins but also the general-purpose output
pins (PS[4:7]) which are not used by SPI.
0 = SPI and/or PS[4:7] output buffers operate normally
1 = SPI and/or PS[4:7] output buffers behave as open-drain
outputs
MSTR — SPI Master/Slave Mode Select
0 = Slave mode
1 = Master mode
When MODF is set, MSTR always reads zero. SP0CR1 must be
written as part of a mode fault recovery sequence.
CPOL, CPHA — SPI Clock Polarity, Clock Phase
These two bits are used to specify the clock format to be used in SPI
operations. When the clock polarity bit is cleared and data is not being
transferred, the SCK pin of the master device is low. When CPOL is
set, SCK idles high. See Figure 16-4 and Figure 16-5.
SSOE — Slave Select Output Enable
The SS output feature is enabled only in the master mode by
asserting the SSOE and DDRS7.
LSBF — SPI LSB First enable
0 = Data is transferred most significant bit first
1 = Data is transferred least significant bit first
Normally data is transferred most significant bit first.This bit does not
affect the position of the MSB and LSB in the data register. Reads and
writes of the data register will always have MSB in bit 7.
MC68HC912DT128A — Rev 4.0
MOTOROLA
Multiple Serial Interface
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Technical Data
295