MC912DG128ACPVE Datasheet, PDF (142/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Resets and Interrupts
IRQEN can be read and written anytime in all modes.
DLY — Enable Oscillator Start-up Delay on Exit from STOP
The delay time of about 4096 cycles is based on the XCLK rate
chosen.
0 = No stabilization delay imposed on exit from STOP mode. A
stable external oscillator must be supplied.
1 = Stabilization delay is imposed before processing resumes after
STOP.
DLY can be read anytime and written once in normal modes. In
special modes, DLY can be read and written anytime.
HPRIO — Highest Priority I Interrupt
RESET:
Bit 7
1
1
6
PSEL6
1
5
PSEL5
1
4
PSEL4
1
3
PSEL3
0
2
PSEL2
0
1
PSEL1
1
Bit 0
0
0
$001F
Write only if I mask in CCR = 1 (interrupts inhibited). Read anytime.
To give a maskable interrupt source highest priority, write the low byte of
the vector address to the HPRIO register. For example, writing $F0 to
HPRIO would assign highest maskable interrupt priority to the real-time
interrupt timer ($FFF0). If an un-implemented vector address or a non-I-
masked vector address (value higher than $F2) is written, then IRQ will
be the default highest priority interrupt.
10.7 Interrupt test registers
These registers are used in special modes for testing the interrupt logic
and priority without needing to know which modules and what functions
are used to generate the interrupts.Each bit is used to force a specific
interrupt vector by writing it to 1.Bits are named with B6 through F4 to
indicate vectors $FFB6 through $FFF4. These bits are also used in
special modes to view that an interrupt caused by a module has reached
the interrupt module.
Technical Data
142
MC68HC912DT128A — Rev 4.0
Resets and Interrupts
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