MC912DG128ACPVE Datasheet, PDF (399/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Development Support
Background Debug Mode
BKGD pin during host-to-target transmissions to speed up rising edges.
Since the target does not drive the BKGD pin during this period, there is
no need to treat the line as an open-drain signal during host-to-target
transmissions.
BDMCLK
(TARGET MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
PERCEIVED
START
OF BIT TIME
SYNCHRONIZATION
UNCERTAINTY
TARGET SENSES BIT
10 CYCLES
Figure 20-1. BDM Host to Target Serial Bit Timing
EARLIEST
START OF
NEXT BIT
HC12A4 BDM HOST TO TARGET TIM
BDMCLK
(TARGET
MCU)
HOST
DRIVE TO
BKGD PIN
TARGET MCU
SPEEDUP PULSE
PERCEIVED
START OF BIT
TIME
BKGD PIN
HIGH-IMPEDANCE
R-C RISE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
10 CYCLES
10 CYCLES
HOST SAMPLES
BKGD PIN
EARLIEST
START OF
NEXT BIT
HC12A4 BDM TARGET TO HOST TIM 1
Figure 20-2. BDM Target to Host Serial Bit Timing (Logic 1)
MC68HC912DT128A — Rev 4.0
MOTOROLA
Development Support
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Technical Data
399