MC912DG128ACPVE Datasheet, PDF (119/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Flash Memory
Operation
PGM — Program Control
This bit configures the memory for program operation. PGM is
interlocked with the ERAS bit such that both bits cannot be equal to 1
or set to1 at the same time.
0 = Program operation is not selected.
1 = Program operation selected.
8.7 Operation
The Flash EEPROM can contain program and data. On reset, it can
operate as a bootstrap memory to provide the CPU with internal
initialization information during the reset sequence.
8.7.1 Bootstrap Operation Single-Chip Mode
After reset, the CPU controlling the system will begin booting up by
fetching the first program address from address $FFFE.
8.7.2 Normal Operation
The Flash EEPROM allows a byte or aligned word read in one bus cycle.
Misaligned word read require an additional bus cycle. The Flash
EEPROM array responds to read operations only. Write operations are
ignored.
8.7.3 Program/Erase Operation
An unprogrammed Flash EEPROM bit has a logic state of one. A bit
must be programmed to change its state from one to zero. Erasing a bit
returns it to a logic one. The Flash EEPROM has a minimum
program/erase life of 100 cycles. Programming or erasing the Flash
EEPROM is accomplished by a series of control register writes.
The Flash EEPROM must be completely erased prior to programming
final data values.
MC68HC912DT128A — Rev 4.0
MOTOROLA
Flash Memory
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Technical Data
119