MC912DG128ACPVE Datasheet, PDF (168/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Clock Functions
Freescale Semiconductor, Inc.
12.6.3 STOP Exit and Fast STOP Recovery
Stop mode is entered when a STOP instruction is executed. Recovery
from STOP depends primarily on the state of the three status bits
NOLHM, CME & DLY.
The DLY bit controls the duration of the waiting period between the
actual exit for some key blocks (e.g. clock monitor, clock generators) and
the effective exit from stop for all the rest of the MCU. DLY=1 enables
the 13-stage counter to generate a 4096 count delay. DLY=0 selects no
delay. As the XCLK is derived from the slow mode divider, the value in
the SLOW register modifies the actual delay time.
NOTE: DLY=0 is only recommended when there is a good signal available
at the EXTAL pin (e.g. an external square wave source).
STOP mode is exited with an external reset, an external interrupt from
IRQ or XIRQ, a Key Wake-Up interrupt from port J or port H, or an
MSCAN Wake-Up interrupt.
EXTALi
Clock Monitor Fail
Limp-Home
13-stage counter
(Clocked by XCLK)
BCSP
0 --> 4096
Restore BCSP
STOP (DLY = 1)
STOP (DLY = 0)
SYSCLK
PLLCLK (L.H.) Restore PLLCLK or EXTALi
Figure 12-5. STOP Exit and Fast STOP Recovery
Technical Data
168
MC68HC912DT128A — Rev 4.0
Clock Functions
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