MC912DG128ACPVE Datasheet, PDF (191/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Clock Functions
Clock Function Registers
Table 12-5. COP Watchdog Rates
CR2 CR1 CR0
Divide
XCLK
by
8.0 MHz XCLK
Time-out
Window COP enabled:
Window start
(1)
Window end
Effective
Window ⁽²⁾
0
0
0
OFF
OFF
OFF
OFF
OFF
0
0
1
2 ¹³
1.024 ms -0/+0.256 ms
0.768 ms
0.768 ms
0 % ⁽³⁾
0
1
0
2 ¹⁵
4.096 ms -0/+0.256 ms
3.072 ms
3.840 ms
18.8 %
0
1
1
2 ¹⁷
16.384 ms -0/+0.256 ms
12.288 ms
16.128 ms
23.4 %
1
0
0
2 ¹⁹
65.536 ms -0/+1.024 ms
49.152 ms
64.512 ms
23.4 %
1
0
1
2 ²¹
262.144 ms -0/+1.024 ms 196.608 ms
261.120 ms
24.6 %
1
1
0
2 ²²
524.288 ms -0/+1.024 ms 393.216 ms
523.264 ms
24.8 %
1
1
1
2 ^{23 1.048576 ms -0/+1.024 ms 786.432 ms}
1.047552 s
24.9 %
1. Time for writing $55 following previous COP restart of time-out logic due to writing $AA.
2. Please refer to WCOP bit description above.
3. Window COP cannot be used at this rate.
DISR — Disable Resets from COP Watchdog and Clock Monitor
Writes are not allowed in normal modes, anytime in special modes.
Read anytime.
0 = Normal operation.
1 = Regardless of other control bit states, COP and clock monitor
will not generate a system reset.
CR2, CR1, CR0 — COP Watchdog Timer Rate select bits
These bits select the COP time-out rate. The clock used for this
module is the XCLK.
Write once in normal modes, anytime in special modes. Read
anytime.
MC68HC912DT128A — Rev 4.0
MOTOROLA
Clock Functions
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Technical Data
191