MC912DG128ACPVE Datasheet, PDF (474/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Revision History
Freescale Semiconductor, Inc.
Section
Page (in Rev 3.0)
Description of change
EEPROM Memory
128, 129
132
FPOPEN bit added to EEMCR register
Paragraph added to the EEPGM description to clarify block
protection
159
Note added about consideration of crystal selection due to EMC
emissions
Clock Functions
159
Opening paragraphs of PLL description changed for clarification
163
In the section on clock loss during normal operation, description of
operation in limp home mode has been expanded for clarification
182
In Figure 12-6, MSCAN clock source selection via CLKSRC bit
corrected
MSCAN Controller
339
First two bullets of sleep mode description updated
352
SLPRQ = 1 description updated
Analog-to-Digital
Converter
Major rewrite of entire section for clarification
Development Support
Clock for the BDM has been renamed as BDMCLK, to
differentiaite it from another internal signal, BCLK
425
Units for I_OFF corrected to nA
Electrical
Specifications
Reference to supply differential voltage values updated.
427
V_REF differential voltage row removed
Analog input differential voltage row added
429
f_XTAL removed
429
Footnote added restricting external oscillator operating frequency
to 8MHz when using a quartz crystal
440
Table footnote removed from Table 21-16 regarding V_DDPLL
Appendix: Changes
from
MC68HC912DG128
444
Additional paragraphs added describing ATD differences from the
non A suffix device
Appendix: CGM
Practical Aspects
Section 23.3 A Few Hints For The CGM Crystal Oscillator
447
Application removed. All points are covered in new Oscillator
section
455
Extra bullets added
Appendix: Information
on
MC68HC912DT128A
Mask Set Changes
New Section
Technical Data
474
MC68HC912DT128A — Rev 4.0
Revision History
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA