MC912DG128ACPVE Datasheet, PDF (379/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Analog-to-Digital Converter
ATD Registers
exited, the ATD module powers up and continues operation. The
module is not reset; the register file is not reinitialized; the conversion
sequence is not restarted.
When the module comes out of wait, it is recommended that a
stabilization delay ( t_SR) is allowed before new conversions are
started.
DJM — Result Register Data Justification Mode
0 = Left justified mode
1 = Right justified mode
For 10-bit resolution, left justified mode maps a result register into
data bus bits 6 through 15; bit 15 is the MSB. In right justified mode,
the result registers maps onto data bus bits 0 through 9; bit 9 is the
MSB.
For 8-bit resolution, left justified mode maps a result into the high byte
(bits 8 though 15; bit 15 is the MSB). Right justified maps a result into
the low byte (bits 0 through 7; bit 7 is the MSB).
Table 19-1 summarizes the result data formats available and how
they are set up using the control bits.
Table 19-2 illustrates left justified output codes for an input signal
range between 0 and 5.1 Volts.
RES10
0
0
1
1
DJM
0
1
0
1
Result Data Formats
Description and Bus Bit Mapping
8-bit/left justified - bits 8-15
8-bit/right justified - bits 0-7
10-bit/left justified - bits 6-15
10-bit/right justified - bits 0-9
Table 19-1. Result Data Formats Available
MC68HC912DT128A — Rev 4.0
MOTOROLA
Analog-to-Digital Converter
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Technical Data
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