MC912DG128ACPVE Datasheet, PDF (158/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Clock Functions
Freescale Semiconductor, Inc.
12.3 Clock Sources
A compatible external clock signal can be applied to the EXTAL pin or
the MCU can generate a clock signal using an on-chip oscillator circuit
and an external crystal or ceramic resonator. The MCU uses several
types of internal clock signals derived from the primary clock signal:
TxCLK clocks are used by the CPU.
ECLK and PCLK are used by the bus interfaces, SPI, PWM, ATD0 and
ATD1.
MCLK is either PCLK or XCLK, and drives on-chip modules such as
SCI0, SCI1 and ECT.
XCLK drives on-chip modules such as RTI, COP and restart-from-stop
delay time.
SLWCLK is used as a calibration output signal.
The MSCAN module is clocked by EXTALi or SYSCLK, under control of
an MSCAN bit.
The clock monitor is clocked by EXTALi.
The BDM system is clocked by BCLK or ECLK, under control of a BDM
bit.
A slow mode clock divider is included to deliver a lower clock frequency
for the SCI baud rate generators, the ECT timer module, and the RTI and
COP clocks. The slow clock bus frequencies divide the crystal frequency
in a programmable range of 4 to 252, with steps of 4. This is very useful
for low power operation.
See the Clock Divider Chains section for further details. Figure 12-1
shows some of the timing relationships.
Technical Data
158
MC68HC912DT128A — Rev 4.0
Clock Functions
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