MC912DG128ACPVE Datasheet, PDF (361/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
MSCAN Controller
Programmer’s Model of Control Registers
0 = The associated message buffer is full (loaded with a message
due for transmission).
1 = The associated message buffer is empty (not scheduled).
NOTE: The CTFLG register is held in the reset state if the SFTRES bit in
CMCR0 is set.
18.13.9 msCAN12 Transmitter Control Register (CTCR)
Bit 7
6
5
4
3
CTCR R
0
0
ABTRQ2 ABTRQ1 ABTRQ0
$0107 W
RESET
0
0
0
0
0
2
TXEIE2
0
1
TXEIE1
0
Bit 0
TXEIE0
0
ABTRQ2 – ABTRQ0 — Abort Request
The CPU sets this bit to request that an already scheduled message
buffer (TXE = 0) shall be aborted. The msCAN12 will grant the
request when the message is not already under transmission. When
a message is aborted the associated TXE and the abort acknowledge
flag (ABTAK, see msCAN12 Transmitter Flag Register (CTFLG)) will
be set and an TXE interrupt will occur if enabled. The CPU can not
reset ABTRQx. ABTRQx is reset implicitly whenever the associated
TXE flag is set.
0 = No abort request.
1 = Abort request pending.
NOTE: The software must not clear one or more of the TXE flags in CTFGL and
simultaneously set the respective ABTRQ bit(s).
TXEIE2 – TXEIE0 — Transmitter Empty Interrupt Enable
0 = No interrupt will be generated from this event.
1 = A transmitter empty (transmit buffer available for transmission)
event will result in a transmitter empty interrupt.
NOTE: The CTCR register is held in the reset state if the SFTRES bit in CMCR0
is set.
MC68HC912DT128A — Rev 4.0
MOTOROLA
MSCAN Controller
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Technical Data
361