MC912DG128ACPVE Datasheet, PDF (255/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Enhanced Capture Timer
Timer Register Descriptions
TQCR — Reserved
$0087
Bit 7
6
5
4
3
2
1
Bit 0
RESET:
0
0
0
0
0
0
0
0
TCTL1 — Timer Control Register 1
Bit 7
6
5
4
3
2
1
Bit 0
OM7
OL7
OM6
OL6
OM5
OL5
OM4
OL4
RESET:
0
0
0
0
0
0
0
0
TCTL2 — Timer Control Register 2
Bit 7
6
5
4
3
2
1
Bit 0
OM3
OL3
OM2
OL2
OM1
OL1
OM0
OL0
RESET:
0
0
0
0
0
0
0
0
$0088
$0089
Read or write anytime.
OMn — Output Mode
OLn — Output Level
These eight pairs of control bits are encoded to specify the output
action to be taken as a result of a successful OCn compare. When
either OMn or OLn is one, the pin associated with OCn becomes an
output tied to OCn regardless of the state of the associated DDRT bit.
NOTE:
To enable output action by OMn and OLn bits on timer port, the
corresponding bit in OC7M should be cleared.
Table 15-1. Compare Result Output Action
OMn
0
0
1
1
OLn
0
1
0
1
Action
Timer disconnected from output pin logic
Toggle OCn output line
Clear OCn output line to zero
Set OCn output line to one
To operate the 16-bit pulse accumulators A and B (PACA and PACB)
independently of input capture or output compare 7 and 0 respectively
the user must set the corresponding bits IOSn = 1, OMn = 0 and OLn
= 0. OC7M7 or OC7M0 in the OC7M register must also be cleared.
MC68HC912DT128A — Rev 4.0
MOTOROLA
Enhanced Capture Timer
For More Information On This Product,
Go to: www.freescale.com
Technical Data
255