MC912DG128ACPVE Datasheet, PDF (405/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

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Background Debug Mode
SHADOW word (location $0FC0); otherwise some regular
EEPROM array locations will not be visible. At the next reset, the
high byte of the SHADOW word is loaded into the EEMCR
register. NOBDML bit in EEMCR will be cleared and BDM will not
be operational.
4. Protect the SHADOW word by setting SHPROT bit in EEPROT
register.
20.4.4.2 Disabling the BDM lockout
Disabling the BDM lockout is only possible in special modes
(SMODN=0) except in special single chip. Follow the same steps as for
enabling the BDM lockout, but erase the SHADOW word.
At the next reset, the high byte of SHADOW word is loaded into the
EEMCR register. NOBDML bit in EEMCR will be set and BDM becomes
operational.
NOTE: When the BDM lockout is enabled it is not possible to run code from the
reset vector in special single chip mode.
20.4.5 BDM Registers
Seven BDM registers are mapped into the standard 64-Kbyte address
space when BDM is active. Mapping is shown in Table 20-4.
Table 20-4. BDM registers
Address
$FF00
$FF01
$FF02 – $FF03
$FF04 – $FF05
$FF06
Register
BDM Instruction Register
BDM Status Register
BDM Shift Register
BDM Address Register
BDM CCR Holding Register
The content of the INSTRUCTION register is determined by the type of
background command being executed.The STATUS register indicates
BDM operating conditions.The SHIFT register contains data being
received or transmitted via the serial interface. The ADDRESS register
MC68HC912DT128A — Rev 4.0
MOTOROLA
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Technical Data
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