MC912DG128ACPVE Datasheet, PDF (166/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Clock Functions
Freescale Semiconductor, Inc.
12.6.2 No Clock at Power-On Reset
The voltage level on VDDPLL determines how the MCU responds to an
external clock loss in this case.
With the VDDPLL supply voltage at VDD level, any reset sets the Clock
Monitor Enable bit (CME) and the PLLON bit and clears the NOLHM bit.
Therefore, if the MCU is powered up without an external clock, limp-
home mode is entered provided the MCU is in a normal mode of
operation.
VDD
Power-On Detector
EXTALi
Clock Monitor Fail
(Slow EXTALi)
Limp-Home
13-stage counter
(Clocked by XCLK)
BCSP
Internal reset
0 --> 4096
0 --> 4096
Reset: BCSP = 0
SYSCLK
PLLCLK (L.H.)
EXTALi
SYSCLK
(Slow EXTALi)
PLLCLK (Software check of Limp-Home Flag)
Figure 12-4. No Clock at Power-On Reset
EXTALi
Technical Data
166
MC68HC912DT128A — Rev 4.0
Clock Functions
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