MC912DG128ACPVE Datasheet, PDF (54/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Pinout and Signal Descriptions
3.4.15 Clock generation module test (CGMTST)
The CGMTST pin (PE6) is the output of the clocks tested when CGMTE
bit is set in PEAR register. The PIPOE bit must be cleared for the clocks
to be tested.
3.4.16 TEST
This pin is used for factory test purposes. It is recommended that this
pin is not connected in the application, but it may be bonded to 5.5 V max
without issue. Never apply voltage higher than 5.5 V to this pin
Table 3-2. MC68HC912DT128A Signal Description Summary
Pin Name
Shared
port
Pin
Number
112-pin
Description
EXTAL
-
47 Crystal driver and external clock input pins. On reset all the device clocks are
XTAL
-
48
derived from the EXTAL input frequency. XTAL is the crystal output.
An active low bidirectional control signal, RESET acts as an input to initialize the
RESET
-
46
MCU to a known start-up state, and an output when COP or clock monitor
causes a reset.
ADDR[7:0]
DATA[7:0]
ADDR[15:8]
DATA[15:8]
PB[7:0]
PA[7:0]
31–24 External bus pins share function with general-purpose I/O ports A and B. In
single chip modes, the pins can be used for I/O. In expanded modes, the pins
64–57 ^{are used for the external buses.}
DBE
PE7
36
Data bus control and, in expanded mode, enables the drive control of external
buses during external reads.
ECLK
PE7
36 Inverted E clock used to latch the address.
CAL is the output of the Slow Mode programmable clock divider, SLWCLK, and
CAL
PE7
36
is used as a calibration reference for functions such as time of day. It is
overridden when DBE function is enabled. It always has a 50% duty.
CGMTST PE6
37 Clock generation module test output.
MODB/IPIP
E1,
MODA/IPIP
PE6, PE5
E0
State of mode select pins during reset determine the initial operating mode of
37, 38 the MCU. After reset, MODB and MODA can be configured as instruction
queue tracking signals IPIPE1 and IPIPE0 or as general-purpose I/O pins.
ECLK
PE4
39
E Clock is the output connection for the external bus clock. ECLK is used as a
timing reference and for address demultiplexing.
Low byte strobe (0 = low byte valid), in all modes this pin can be used as I/O.
LSTRB/TA
GLO
PE3
53
The low strobe function is the exclusive-NOR of A0 and the internal SZ8
signal. (The SZ8 internal signal indicates the size 16/8 access.) Pin function
TAGLO used in instruction tagging. See Development Support.
R/W
PE2
54
Indicates direction of data on expansion bus. Shares function with general-
purpose I/O. Read/write in expanded modes.
Technical Data
54
MC68HC912DT128A — Rev 4.0
Pinout and Signal Descriptions
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