MC912DG128ACPVE Datasheet, PDF (270/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Enhanced Capture Timer
0 = Queue Mode of Input Capture is enabled.
The main timer value is memorized in the IC register by a valid
input pin transition.
With a new occurrence of a capture, the value of the IC register
will be transferred to its holding register and the IC register
memorizes the new timer value.
1 = Latch Mode is enabled. Latching function occurs when
modulus down-counter reaches zero or a zero is written into
the count register MCCNT (see Buffered IC Channels).
With a latching event the contents of IC registers and 8-bit
pulse accumulators are transferred to their holding registers.
8-bit pulse accumulators are cleared.
TIMTST — Timer Test Register
$00AD
BIT 7
6
5
4
3
2
1
BIT 0
0
0
0
0
0
0
TCBYP
0
RESET:
0
0
0
0
0
0
0
0
Read: any time
Write: only in special mode (SMOD = 1).
TCBYP — Main Timer Divider Chain Bypass
0 = Normal operation
1 = For testing only. The 16-bit free-running timer counter is divided
into two 8-bit halves and the prescaler is bypassed. The clock
drives both halves directly.
When the high byte of timer counter TCNT ($84) overflows
from $FF to $00, the TOF flag in TFLG2 ($8F) will be set.
PORTT — Timer Port Data Register
BIT 7
6
5
PORT
PT7
PT6
PT5
TIMER
I/OC7
I/OC6
I/OC5
RESET:
-
-
-
4
PT4
I/OC4
-
3
PT3
I/OC3
-
2
PT2
I/OC2
-
1
PT1
I/OC1
-
BIT 0
PT0
I/OC0
-
$00AE
Read: any time (inputs return pin level; outputs return data register
contents)
Technical Data
270
MC68HC912DT128A — Rev 4.0
Enhanced Capture Timer
For More Information On This Product,
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