MC912DG128ACPVE Datasheet, PDF (237/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Pulse Width Modulator
PWM Register Descriptions
PWCTL — PWM Control Register
Bit 7
6
5
0
0
0
RESET:
0
0
0
4
PSWAI
0
3
CENTR
0
2
RDPP
0
1
PUPP
0
Bit 0
PSBCK
0
$0054
Read and write anytime.
PSWAI — PWM Halts while in Wait Mode
0 = Allows PWM main clock generator to continue while in wait
mode.
1 = Halt PWM main clock generator when the part is in wait mode.
CENTR — Center-Aligned Output Mode
To avoid irregularities in the PWM output mode, write the CENTR bit
only when PWM channels are disabled.
0 = PWM channels operate in left-aligned output mode
1 = PWM channels operate in center-aligned output mode
RDPP — Reduced Drive of Port P
0 = All port P output pins have normal drive capability.
1 = All port P output pins have reduced drive capability.
PUPP — Pull-Up Port P Enable
0 = All port P pins have an active pull-up device disabled.
1 = All port P pins have an active pull-up device enabled.
PSBCK — PWM Stops while in Background Mode
0 = Allows PWM to continue while in background mode.
1 = Disable PWM input clock when the part is in background mode.
MC68HC912DT128A — Rev 4.0
MOTOROLA
Pulse Width Modulator
For More Information On This Product,
Go to: www.freescale.com
Technical Data
237