MC912DG128ACPVE Datasheet, PDF (145/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Resets and Interrupts
Effects of Reset
software failing to execute the sequence properly causes a COP reset to
occur. In addition, windowed COP operation can be selected. In this
mode, a write to the COPRST register must occur in the last 25% of the
selected period. A premature write will also reset the part.
10.8.4 Clock Monitor Reset
If clock frequency falls below a predetermined limit when the clock
monitor is enabled, a reset occurs.
10.9 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to
known start-up states, as follows.
10.9.1 Operating Mode and Memory Map
Operating mode and default memory mapping are determined by the
states of the BKGD, MODA, and MODB pins during reset. The SMODN,
MODA, and MODB bits in the MODE register reflect the status of the
mode-select inputs at the rising edge of reset. Operating mode and
default maps can subsequently be changed according to strictly defined
rules.
10.9.2 Clock and Watchdog Control Logic
The COP watchdog system is enabled, with the CR[2:0] bits set for the
longest duration time-out. The clock monitor is disabled. The RTIF flag
is cleared and automatic hardware interrupts are masked. The rate
control bits are cleared, and must be initialized before the RTI system is
used. The DLY control bit is set to specify an oscillator start-up delay
upon recovery from STOP mode.
MC68HC912DT128A — Rev 4.0
MOTOROLA
Resets and Interrupts
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Technical Data
145