MC912DG128ACPVE Datasheet, PDF (437/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Electrical Specifications
Tables of Data
Table 21-15. SPI Timing
(V_DD = 5.0 Vdc ±10%, V_SS = 0 Vdc, T_A = T_L to T_H , 200 pF load on all SPI pins)⁽¹⁾
Num
Function
Symbol
Min
Max
Operating Frequency
Master
Slave
f_op
1/256
1/2
1/256
1/2
SCK Period
Master
Slave
t_sck
2
256
2
—
Enable Lead Time
Master
Slave
t_lead
1/2
—
1
—
Enable Lag Time
Master
Slave
t_lag
1/2
—
1
—
Clock (SCK) High or Low Time
Master
Slave
Sequential Transfer Delay
Master
Slave
t_wsck
t_td
t_cyc − 30
t_cyc − 30
1/2
1
128 t_cyc
—
—
—
Data Setup Time (Inputs)
Master
Slave
Data Hold Time (Inputs)
Master
Slave
Slave Access Time
Slave MISO Disable Time
Data Valid (after SCK Edge)
Master
Slave
Data Hold Time (Outputs)
Master
Slave
t_su
30
—
30
—
t_hi
0
—
30
—
t_a
—
1
t_dis
—
1
t_v
—
50
—
50
t_ho
0
—
0
—
Rise Time
Input
Output
Fall Time
Input
Output
t_ri
—
t_cyc − 30
t_ro
—
30
t_fi
—
t_cyc − 30
t_fo
—
30
1. All AC timing is shown with respect to 20% V_DD and 70% V_DD levels unless otherwise noted.
Unit
f_eclk
t_cyc
t_cyc
t_sck
t_cyc
t_sck
t_cyc
ns
ns
t_sck
t_cyc
ns
ns
ns
ns
t_cyc
t_cyc
ns
ns
ns
ns
ns
ns
ns
ns
MC68HC912DT128A — Rev 4.0
MOTOROLA
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
Technical Data
437