MC912DG128ACPVE Datasheet, PDF (176/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Clock Functions
Freescale Semiconductor, Inc.
Bit 7
6
5
4
3
2
1
Bit 0
LOCKIF LOCK
0
0
0
0
LHIF
LHOME
RESET:
0
0
0
0
0
0
0
0
PLLFLG — PLL Flags
$003B
Read anytime, refer to each bit for write conditions.
LOCKIF — PLL Lock Interrupt Flag
0 = No change in LOCK bit.
1 = LOCK condition has changed, either from a locked state to an
unlocked state or vice versa.
To clear the flag, write one to this bit in PLLFLG. Cleared in limp-home
mode.
LOCK — Locked Phase Lock Loop Circuit
Regardless of the bandwidth control mode (automatic or manual):
0 = PLL VCO is not within the desired tolerance of the target
frequency.
1 = After the phase lock loop circuit is turned on, indicates the PLL
VCO is within the desired tolerance of the target frequency.
Write has no effect on LOCK bit. This bit is cleared in limp-home mode as
the lock detector cannot operate without the reference frequency.
LHIF — Limp-Home Interrupt Flag
0 = No change in LHOME bit.
1 = LHOME condition has changed, either entered or exited limp-
home mode.
To clear the flag, write one to this bit in PLLFLG.
LHOME — Limp-Home Mode Status
0 = MCU is operating normally, with EXTALi clock available for
generating clocks or as PLL reference.
1 = Loss of reference clock. CGM delivers PLL VCO limp-home
frequency to the MCU.
For Limp-Home mode, see Limp-Home and Fast STOP Recovery
modes.
Technical Data
176
MC68HC912DT128A — Rev 4.0
Clock Functions
For More Information On This Product,
Go to: www.freescale.com
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