MC912DG128ACPVE Datasheet, PDF (355/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
MSCAN Controller
Programmer’s Model of Control Registers
18.13.5 msCAN12 Bus Timing Register 1 (CBTR1)
CBTR1 R
$0103 W
RESET
Bit 7
SAMP
0
6
TSEG22
0
5
TSEG21
0
4
TSEG20
0
3
TSEG13
0
2
TSEG12
0
1
TSEG11
0
Bit 0
TSEG10
0
SAMP — Sampling
This bit determines the number of samples of the serial bus to be
taken per bit time. If set three samples per bit are taken, the regular
one (sample point) and two preceding samples, using a majority rule.
For higher bit rates SAMP should be cleared, which means that only
one sample will be taken per bit.
0 = One sample per bit.
1 = Three samples per bit⁽¹⁾.
TSEG22 – TSEG10 — Time Segment
Time segments within the bit time fix the number of clock cycles per
bit time, and the location of the sample point.
Table 18-6. Time segment syntax
SYNC_SEG System expects transitions to occur on the bus during this period.
Transmit point
A node in transmit mode will transfer a new value to the CAN bus at
this point.
A node in receive mode will sample the bus at this point. If the three
Sample point samples per bit option is selected then this point marks the position
of the third sample.
Time segment 1 (TSEG1) and time segment 2 (TSEG2) are
programmable as shown in Table 18-7.
Table 18-7. Time segment values
TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1
0
0
0
0
1 Tq clock cycle
0
0
0
1
2 Tq clock cycles
0
0
1
0
3 Tq clock cycles
0
0
1
1
4 Tq clock cycles
.
.
.
.
.
.
.
.
.
.
1
1
1
1 16 Tq clock cycles
TSEG22
0
0
.
.
1
TSEG21
0
0
.
.
1
TSEG20
0
1
.
.
1
Time segment 2
1 Tq clock cycle
2 Tq clock cycles
.
.
8 Tq clock cycles
1. In this case PHASE_SEG1 must be at least 2 TimeQuanta.
MC68HC912DT128A — Rev 4.0
MOTOROLA
MSCAN Controller
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Technical Data
355