MC912DG128ACPVE Datasheet, PDF (201/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Oscillator
MC68HC912Dx128C Colpitts Oscillator Specification
13.4.1.4 Input ESD Resistor Path Modification
To satisfy the condition of oscillation, the oscillator circuit must not only
provide the correct amount of gain but also the correct amount of phase
shift. In the Colpitts configuration, the phase shift due to parasitics in the
input path to the gate of the transconductance amplifier must be as low
as possible. In the original configuration, the parasitic capacitance of the
clock input buffer (OTA), automatic Loop Control circuit (ALC), and input
resistors (RFLT and RFLT2) reacted with the input resistance to cause
a large phase shift.
To reduce the phase shift, the input ESD resistor (marked RESD in the
figure above) was changed from a single path to the input circuitry (the
ALC and the OTA) and oscillator transconductance amplifier (marked
GM in the figure above) to a parallel path. In this configuration, the only
capacitance causing a phase shift on the input to the transconductance
device is due to the transconductance device itself.
13.4.2 MC68HC912Dx128C Oscillator Circuit Specifications
13.4.2.1 Negative Resistance Margin
Negative Resistance Margin (NRM) is a figure of merit commonly used
to qualify an oscillator circuit with a given resonator. NRM is an indicator
of how much additional resistance in series with the resonator is
tolerable while still maintaining oscillation. This figure is usually expected
to be a multiple of the nominal "maximum" rated ESR of the resonator to
allow for variation and degradation of the resonator.
Currently, many systems are optimized for NRM by adjusting the load
capacitors until NRM is maximized. This method may not achieve the
best overall NRM because the optimization method is empirical and not
analytical. That is, the method only achieves the best NRM for the
particular sample set of microcontrollers, resonators, and board values
tested. The figure below shows the anticipated NRM for a nominal 4MHz
resonator given the expected process variance of the microcontroller
(D60A), board, and crystal (excluding ESR). In this case, the value of
load capacitors providing the optimum NRM for a best-case situation
MC68HC912DT128A — Rev 4.0
MOTOROLA
Oscillator
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Technical Data
201