MC912DG128ACPVE Datasheet, PDF (415/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
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Breakpoints
To trace program flow, setting the BKPM bit causes address comparison
of program data only. Control bits are also available that allow checking
read/write matches.
BRKCT0 — Breakpoint Control Register 0
RESET:
Bit 7
BKEN1
0
6
BKEN0
0
5
BKPM
0
4
3
2
1
0
BK1ALE BK0ALE
0
0
0
0
0
Bit 0
0
0
Read and write anytime.
This register is used to control the breakpoint logic.
BKEN1, BKEN0 — Breakpoint Mode Enable
$0020
Table 20-7. Breakpoint Mode Control
BKEN1 BKEN0
Mode Selected
BRKAH/L Usage BRKDH/L Usage R/W
0
0 Breakpoints Off
—
—
—
0
1 SWI — Dual Address Mode
Address Match Address Match No
1
0 BDM — Full Breakpoint Mode Address Match
Data Match
Yes
1
1 BDM — Dual Address Mode Address Match Address Match Yes
Range
—
Yes
Yes
Yes
BKPM — Break on Program Addresses
This bit controls whether the breakpoint will cause a break on a match
(next instruction boundary) or on a match that will be an executable
opcode. Data and non-executed opcodes cannot cause a break if this
bit is set. This bit has no meaning in SWI dual address mode. The
SWI mode only performs program breakpoints.
0 = On match, break at the next instruction boundary
1 = On match, break if the match is an instruction that will be
executed. This uses tagging as its breakpoint mechanism.
BK1ALE — Breakpoint 1 Range Control
Only valid in dual address mode.
0 = BRKDL will not be used to compare to the address bus.
1 = BRKDL will be used to compare to the address bus.
MC68HC912DT128A — Rev 4.0
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Technical Data
415