MC912DG128ACPVE Datasheet, PDF (230/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Pulse Width Modulator
Table 14-1. Clock A and Clock B Prescaler
PCKA2
(PCKB2)
0
0
0
0
1
1
1
1
PCKA1
(PCKB1)
0
0
1
1
0
0
1
1
PCKA0
(PCKB0)
0
1
0
1
0
1
0
1
Value of
Clock A (B)
P
P÷2
P÷4
P÷8
P ÷ 16
P ÷ 32
P ÷ 64
P ÷ 128
PWPOL — PWM Clock Select and Polarity
Bit 7
6
5
PCLK3 PCLK2 PCLK1
RESET:
0
0
0
4
PCLK0
0
3
PPOL3
0
2
PPOL2
0
1
PPOL1
0
Bit 0
PPOL0
0
$0041
Read and write anytime.
PCLK3 — PWM Channel 3 Clock Select
0 = Clock B is the clock source for channel 3.
1 = Clock S1 is the clock source for channel 3.
PCLK2 — PWM Channel 2 Clock Select
0 = Clock B is the clock source for channel 2.
1 = Clock S1 is the clock source for channel 2.
PCLK1 — PWM Channel 1 Clock Select
0 = Clock A is the clock source for channel 1.
1 = Clock S0 is the clock source for channel 1.
PCLK0 — PWM Channel 0 Clock Select
0 = Clock A is the clock source for channel 0.
1 = Clock S0 is the clock source for channel 0.
If a clock select is changed while a PWM signal is being generated, a
truncated or stretched pulse may occur during the transition.
The following four bits apply in left-aligned mode only:
Technical Data
230
MC68HC912DT128A — Rev 4.0
Pulse Width Modulator
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