MC912DG128ACPVE Datasheet, PDF (253/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Enhanced Capture Timer
Timer Register Descriptions
When the OC7Mn bit is set, a successful OC7 action will override a
successful OC[6:0] compare action during the same cycle; therefore, the
OCn action taken will depend on the corresponding OC7D bit.
TCNT — Timer Count Register
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
RESET:
0
0
0
0
0
0
$0084–$0085
1
Bit 0
9
Bit 8
1
Bit 0
0
0
The 16-bit main timer is an up counter.
A full access for the counter register should take place in one clock cycle.
A separate read/write for high byte and low byte will give a different result
than accessing them as a word.
Read anytime.
Write has no meaning or effect in the normal mode; only writable in
special modes (SMODN = 0).
The period of the first count after a write to the TCNT registers may be a
different size because the write is not synchronized with the prescaler
clock.
TSCR — Timer System Control Register
$0086
Bit 7
6
5
4
3
2
1
Bit 0
TEN
TSWAI TSBCK TFFCA
RESET:
0
0
0
0
0
0
0
0
Read or write anytime.
TEN — Timer Enable
0 = Disables the main timer, including the counter. Can be used for
reducing power consumption.
1 = Allows the timer to function normally.
If for any reason the timer is not active, there is no ÷64 clock for the
pulse accumulator since the E÷64 is generated by the timer prescaler.
MC68HC912DT128A — Rev 4.0
MOTOROLA
Enhanced Capture Timer
For More Information On This Product,
Go to: www.freescale.com
Technical Data
253