MC912DG128ACPVE Datasheet, PDF (275/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Enhanced Capture Timer
Timer and Modulus Counter Operation in Different Modes
Read: any time
Write: has no effect.
These registers are used to latch the value of the input capture registers
TC0 – TC3. The corresponding IOSx bits in TIOS ($80) should be
cleared (see IC Channels).
15.5 Timer and Modulus Counter Operation in Different Modes
STOP:
Timer and modulus counter are off since clocks are
stopped.
BGDM:
Timer and modulus counter keep on running, unless
TSBCK (REG$86, bit5) is set to one.
WAIT:
Counters keep on running, unless TSWAI in TSCR ($86)
is set to one.
NORMAL:
Timer and modulus counter keep on running, unless TEN
in TSCR($86) respectively MCEN in MCCTL ($A6) are
cleared.
TEN=0:
All 16-bit timer operations are stopped, can only access
the registers.
MCEN=0: Modulus counter is stopped.
PAEN=1: 16-bit Pulse Accumulator A is active.
PAEN=0: 8-Bit Pulse Accumulators 3 and 2 can be enabled. (see
ICPAR)
PBEN=1: 16-bit Pulse Accumulator B is active.
PBEN=0: 8-Bit Pulse Accumulators 1 and 0 can be enabled. (see
ICPAR)
MC68HC912DT128A — Rev 4.0
MOTOROLA
Enhanced Capture Timer
For More Information On This Product,
Go to: www.freescale.com
Technical Data
275