MC912DG128ACPVE Datasheet, PDF (108/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Bus Control and Input/Output
PEAR — Port E Assignment Register
$000A
RESET:
RESET:
RESET:
RESET:
RESET:
BIT 7
NDBE
0
0
1
1
0
6
CGMTE
0
0
1
0
0
5
PIPOE
0
1
0
0
1
4
NECLK
0
0
1
1
0
3
LSTRE
0
1
0
0
1
2
RDWE
0
1
0
0
1
1
CALE
0
0
0
0
0
BIT 0
DBENE
0
0
0
0
0
Normal Ex-
panded
Special Ex-
panded
Peripheral
Normal sin-
gle chip
Special sin-
gle chip
Port E serves as general purpose I/O lines or as system and bus
control signals. The PEAR register is used to choose between the
general-purpose I/O functions and the alternate bus control functions.
When an alternate control function is selected, the associated DDRE
bits are overridden.
The reset condition of this register depends on the mode of operation
because bus control signals are needed immediately after reset in
some modes.
In normal single-chip mode, no external bus control signals are
needed so all of port E is configured for general-purpose I/O.
In normal expanded modes, the reset vector is located in external
memory. The DBE and E clock are required for de-multiplexing
address and data but LSTRB and R/W are only needed by the system
when there are external writable resources. Therefore in normal
expanded modes, the DBE and the E clock are configured for their
alternate bus control functions and the other bits of port E are
configured for general-purpose I/O. If the normal expanded system
needs any other bus control signals, PEAR would need to be written
before any access that needed the additional signals.
In special expanded modes, DBE, IPIPE1, IPIPE0, E, LSTRB, and
R/W are configured as bus-control signals.
In special single chip modes, DBE, IPIPE1, IPIPE0, E, LSTRB, R/W,
and CALE are configured as bus-control signals.
Technical Data
108
MC68HC912DT128A — Rev 4.0
Bus Control and Input/Output
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