MC912DG128ACPVE Datasheet, PDF (353/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
MSCAN Controller
Programmer’s Model of Control Registers
18.13.3 msCAN12 Module Control Register (CMCR1)
Bit 7
6
5
4
3
CMCR1 R
0
0
0
0
0
$0101 W
RESET
0
0
0
0
0
2
LOOPB
0
1
WUPM
0
Bit 0
CLKSRC
0
LOOPB — Loop Back Self Test Mode
When this bit is set the msCAN12 performs an internal loop back
which can be used for self test operation: the bit stream output of the
transmitter is fed back to the receiver. The RxCAN input pin is ignored
and the TxCAN output goes to the recessive state (1). Note that in this
state the msCAN12 ignores the bit sent during the ACK slot of the
CAN frame Acknowledge field to insure proper reception of its own
message and will treat messages being received while in
transmission as received messages from remote nodes.
0 = Normal operation
1 = Activate loop back self test mode
WUPM — Wake-Up Mode
This flag defines whether the integrated low-pass filter is applied to
protect the msCAN12 from spurious wake-ups (see Programmable
Wake-Up Function).
0 = msCAN12 will wake up the CPU after any recessive to
dominant edge on the CAN bus.
1 = msCAN12 will wake up the CPU only in case of dominant pulse
on the bus which has a length of at least approximately T_wup.
CLKSRC — msCAN12 Clock Source
This flag defines which clock source the msCAN12 module is driven
from (only for system with CGM module; see Clock System, Figure
18-7).
0 = The msCAN12 clock source is EXTALi.
1 = The msCAN12 clock source is SYSCLK, twice the frequency of
ECLK.
NOTE: The CMCR1 register can only be written if the SFTRES bit in CMCR0 is
set.
MC68HC912DT128A — Rev 4.0
MOTOROLA
MSCAN Controller
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Technical Data
353