MC912DG128ACPVE Datasheet, PDF (445/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Appendix: Changes from MC68HC912DG128
Significant changes from the MC68HC912DG128 (non-suffix device)
22.2.7.3 Additional Features
ATD flexibility has been increased with additional signed result, data
justification, single conversion selection and results location FIFO
features.
DJM & DSGN bits have been added to ATDxCTL2 register. Default
values are compatible with MC68HC912DG128 functionality.
FIFO & S1C bits have been added to ATDxCTL3 register. Default values
are compatible with MC68HC912DG128 functionality.
22.2.7.4 S8CM bit
Bit S8CM in ATDxCTL5 is renamed S8C. Functionality is compatible
with S8CM but can now be modified by the new S1C bit in ATDxCTL3.
The default is compatible with MC68HC912DG128 functionality.
22.2.7.5 Writing to ATDxCTL4
Writing to ATDxCTL4 aborts any ongoing conversion sequence and
initiates a new conversion sequence. Previously it only aborted ongoing
sequences leaving the ATD in idle mode (no conversion sequences
being processed). Writing to ATDxCTL2 or ADTxCTL3 also does not
abort an ongoing conversion sequence. Previously writing these
registers also aborted any ongoing sequence leaving the ATD in idle
mode .
This is unlikely to be a compatibility issue as applications mostly write
these registers to configure the ATD, closely followed by a write to
ATDxCTL5 to initiate a new conversion sequence which does abort any
ongoing conversion sequence and resets the appropriate flags.
To ensure compatibility, the application should not rely on ongoing
conversions being aborted. Also any interrupts from the completion of an
ongoing sequence should be masked and/or handled correctly.
MC68HC912DT128A — Rev 4.0
MOTOROLA
Appendix: Changes from MC68HC912DG128
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Technical Data
445