MC912DG128ACPVE Datasheet, PDF (352/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
MSCAN Controller
SLPRQ — SLEEP request
This flag allows to request the msCAN12 to go into an internal power-
saving mode (see msCAN12 SLEEP Mode).
0 = Wake-up – The msCAN12 will function normally.
1 = SLEEP request – The msCAN12 will go into SLEEP Mode
when the CAN bus is idle, i.e. the module is not receiving a
message and all transmit buffers are empty.
SFTRES— SOFT_RESET
When this bit is set by the CPU, the msCAN12 immediately enters the
SOFT_RESET state. Any ongoing transmission or reception is
aborted and synchronization to the bus is lost.
The following registers will go into and stay in the same state as out
of hard reset: CMCR0, CRFLG, CRIER, CTFLG, CTCR.
The registers CMCR1, CBTR0, CBTR1, CIDAC, CIDAR0–3,
CIDMR0–3 can only be written by the CPU when the msCAN12 is in
SOFT_RESET state. The values of the error counters are not affected
by SOFT_RESET.
When this bit is cleared by the CPU, the msCAN12 will try to
synchronize to the CAN bus: If the msCAN12 is not in BUSOFF state
it will be synchronized after 11 recessive bits on the bus; if the
msCAN12 is in BUSOFF state it continues to wait for 128 occurrences
of 11 recessive bits.
Clearing SFTRES and writing to other bits in CMCR0 must be in
separate instructions.
0 = Normal operation
1 = msCAN12 in SOFT_RESET state.
Technical Data
352
MC68HC912DT128A — Rev 4.0
MSCAN Controller
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